Protection circuit

ABSTRACT

A semiconductor device includes first to fifth regions, first and second resistive loads. The first region is coupled to a first reference voltage terminal. The first to third regions operate as a first transistor. The fourth region is coupled to a second reference voltage terminal. The fourth to fifth regions operate as a second transistor. The first resistive load couples the second region to the second reference voltage terminal. The second resistive load couples the fifth region to the first reference voltage terminal. The first, third, second, fifth and fourth regions are arranged in order, each of the first, second and third regions corresponds to a first conductive type, and each of the fourth and fifth regions corresponds to a second conductive type.

The present application is a continuation application of U.S.application Ser. No. 16/886,586, filed on May 28, 2020, which is acontinuation application of U.S. application Ser. No. 15/725,246, filedon Oct. 4, 2017, now U.S. Pat. No. 10,679,981, issued Jun. 9, 2020,which claims priority benefit of U.S. Provisional Application Ser. No.62/479,234, filed Mar. 30, 2017, the full disclosures of which areincorporated herein by reference.

BACKGROUND

Latch-up is a general problem associated with CMOS structure thatinduces an undesirable conduction mechanism. CMOS integrated circuitsinclude parasitic P/N/P/N structures that have the latch-up problem whenone of the junctions in the P/N/P/N structures is forward biased. Aguard ring structure and/or a pick-up structure are applied to the CMOSintegrated circuits to prevent the latch-up problem, but the guard ringstructure and/or the pick-up structure consume large layout area.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a schematic diagram of a circuit in accordance with someembodiments of the present disclosure;

FIG. 2 is a schematic diagram of a circuit in accordance with some otherembodiments of the present disclosure;

FIG. 3 is a schematic diagram of a circuit in accordance with variousembodiments of the present disclosure;

FIG. 4 is a cross-sectional diagram of a semiconductor device of thecircuit in FIG. 3, in accordance with some embodiments of the presentdisclosure;

FIG. 5 is a cross-sectional diagram of a portion of the semiconductordevice in FIG. 4, together with a resistive load, in accordance withsome embodiments of the present disclosure;

FIG. 6 is a cross-sectional diagram of a portion of the semiconductordevice in FIG. 4, together with a resistive load, in accordance withsome other embodiments of the present disclosure;

FIG. 7 is a cross-sectional diagram of a portion of the semiconductordevice in FIG. 4, together with a resistive load, in accordance withalternative embodiments of the present disclosure;

FIG. 8 is a cross-sectional diagram of a portion of the semiconductordevice in FIG. 4, together with a resistive load, in accordance withvarious embodiments of the present disclosure; and

FIG. 9 is a flow chart illustrating a method applied to the circuitsillustrated in FIGS. 1-3 or the semiconductor devices illustrated inFIGS. 4-8, in accordance with various embodiments of the presentdisclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components, materials, values, steps,arrangements or the like are described below to simplify the presentdisclosure. These are, of course, merely examples and are not intendedto be limiting. Other components, materials, values, steps, arrangementsor the like are contemplated. For example, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed between the first and second features, such thatthe first and second features may not be in direct contact. In addition,the present disclosure may repeat reference numerals and/or letters inthe various examples. This repetition is for the purpose of simplicityand clarity and does not in itself dictate a relationship between thevarious embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. The term mask,photolithographic mask, photomask and reticle are used to refer to thesame item.

The terms used in this specification generally have their ordinarymeanings in the art and in the specific context where each term is used.The use of examples in this specification, including examples of anyterms discussed herein, is illustrative only, and in no way limits thescope and meaning of the disclosure or of any exemplified term.Likewise, the present disclosure is not limited to various embodimentsgiven in this specification.

It will be understood that, although the terms “first,” “second,” etc.,may be used herein to describe various elements, these elements shouldnot be limited by these terms. These terms are used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the embodiments. As usedherein, the term “and/or” includes any and all combinations of one ormore of the associated listed items.

As used herein, the terms “comprising,” “including,” “having,”“containing,” “involving,” and the like are to be understood to beopen-ended, that is, to mean including but not limited to.

Reference is made to FIG. 1. FIG. 1 is a schematic diagram of a circuit100 in accordance with various embodiments of the present disclosure.The circuit 100 includes transistors Q1 and Q2, resistors R1 and R2, anda resistive load 110. In some embodiments, the transistor Q1 has fourterminals, and the transistor Q2 has three terminals. For illustration,the transistor Q1 has a base B1 coupled to a reference voltage terminalVDD through the resistor R1, an emitter E1 coupled to the referencevoltage terminal VDD, a first collector C11 coupled through the resistorR2 to a reference voltage terminal VSS, and a second collector C12coupled to the reference voltage terminal VSS through the resistive load110. The transistor Q2 has a base B2 coupled to the resistor R2 and thefirst collector C11 of the transistor Q1, an emitter E2 coupled to thereference voltage terminal VSS, and a collector C2 coupled to the baseB1 of the transistor Q1 and to the reference voltage terminal VDDthrough the resistor R1. Explained in a different way, the transistor Q1has two collectors C11 and C12, and the transistor Q2 has one collectorC2. The transistors Q1 and Q2 are coupled together to operate as asilicon controlled rectifier (SCR).

In some embodiments, the transistor Q1 is a PNP bipolar junctiontransistor (BJT), and the transistor Q2 is a NPN bipolar junctiontransistor.

For illustration of operation with respect to the circuit 100 in FIG. 1,when a trigger source (not shown) is generated to turn on the transistorQ1, minority carriers are injected from the base-emitter (B1-E1)junction of the transistor Q1. The minority carriers are dischargedthrough the first collector C11 of the transistor Q1 and the resistor R2to the reference voltage terminal VSS, and also through the secondcollector C12 of the transistor Q1 and the resistive load 110 to thereference voltage terminal VSS. When the minority carriers aredischarged through the first collector C11 and the second collector C12of the transistor Q1, a current IC1 and a current IC2 are generatedaccordingly. With the current IC1 flowing through the resistor R2, avoltage at the base B2 of the transistor Q2 is generated. If thebase-emitter voltage VBE of the transistor Q2 is sufficient for thetransistor Q2 to turn on, the transistor Q2 will be turned on, and thusa silicon controlled rectifier (SCR) including the transistors Q1 and Q2will be turned on.

In some approaches, minority carriers are mostly discharged through apath including, for example, the first collector C11 of the transistorQ1 as illustrated in FIG. 1. Accordingly, a parasitic SCR in integratedcircuits is easily turned on in a way as discussed above. As a result,the integrated circuits including the parasitic SCR can be easilyconducted in an undesired condition (also referred to as “latch-up” insome approaches), which leads to the destruction of the integratedcircuits in some situations.

Compared to the above approaches, to discharge the minority carriers, ashunt path including, for illustration in FIG. 1, the second collectorC12 of the transistor Q1 and the resistive load 110 is provided in theembodiments of the present application. As discussed above, the currentIC2 flowing through the shunt path is also generated when the minoritycarriers are discharged. With the generated current IC2, the current IC1is reduced compared to related approaches. As a result, the voltagerequired to turn on the transistor Q2 in FIG. 1 increases. Accordingly,a voltage for turning on the SCR which includes the transistors Q1 andQ2 increases as well, and the SCR will not be easily turned on in anundesired condition. The above voltage used for the SCR is also referredto as a holding voltage in some embodiments, which indicates a voltagesufficient for the SCR to remain turn-on. As a result, integratedcircuits including the SCR will not be conducted in an undesiredcondition, and will be prevented from being destructed due to undesiredoperation. Latch-up immunity for the integrated circuits including theSCR is thus improved.

The resistive load 110 and the collectors C11 and C12 of the transistorQ1 in the circuit 100 in FIG. 1 are given for illustrative purposes.Various numbers of resistive loads and collectors of the transistor Q1in the circuit 100 are within the contemplated scope of the presentdisclosure.

In alternative embodiments, the transistor Q2 has four terminals, andthe transistor Q1 has three terminals. Reference is made to FIG. 2. FIG.2 is a schematic diagram of a circuit 200 in accordance with variousembodiments of the present disclosure. With respect to the embodimentsof FIG. 2, like elements in FIG. 1 are designated with the samereference numbers for ease of understanding. The circuit 200 includestransistors Q1 and Q2, the resistors R1 and R2, and a resistive load220. For illustration, compared to the circuit 100 in FIG. 1, thetransistor Q1 has merely one collector C1 coupled to the referencevoltage terminal VSS through the resistor R2, and the transistor Q2 hasa first collector C21 coupled to the base B1 of the transistor Q1 andthe resistor R1, and a second collector C22 coupled to the referencevoltage terminal through the resistive load 220. Explained in adifferent way, the transistor Q2 has two collectors C21 and C22, and thetransistor Q1 has one collector C1. Similar to the circuit 100, thetransistors Q1 and Q2 operate as a silicon controlled rectifier (SCR).

For illustration of operation with respect to the circuit 200 in FIG. 2,when a trigger source (not shown) is generated to turn on the transistorQ2, minority carriers are injected from the base-emitter (B2-E2)junction of the transistor Q2. The minority carriers are dischargedthrough the first collector C21 of the transistor Q2 and the resistor R1to the reference voltage terminal VDD, and also through the secondcollector C22 of the transistor Q2 and the resistive load 220 to thereference voltage terminal VDD. When the minority carriers aredischarged through the first collector C21 and the second collector C22of the transistor Q2, a current IC1 and a current IC2 are generatedaccordingly. With the current IC1 flowing through the resistor R1, avoltage at the base B1 of the transistor Q1 is generated. If thebase-emitter voltage VBE of the transistor Q1 is sufficient for thetransistor Q1 to turn on, the transistor Q1 will be turned on, and thusa silicon controlled rectifier (SCR) including the transistors Q1 and Q2will be turned on.

In some approaches, minority carriers are mostly discharged through apath including, for example, the first collector C21 of the transistorQ2 as illustrated in FIG. 2. Accordingly, a parasitic SCR in integratedcircuits is easily turned on in a way as discussed above. As a result,the integrated circuits including the parasitic SCR can be easilyconducted in an undesired condition (also referred to as “latch-up” insome approaches), which leads to the destruction of the integratedcircuits in some situations.

Compared to the above approaches, to discharge the minority carriers, ashunt path including, for illustration in FIG. 2, the second collectorC22 of the transistor Q2 and the resistive load 220 are provided in theembodiments of the present application. As discussed above, the currentIC2 flowing through the shunt path is also generated when the minoritycarriers are discharged. With the generated current IC2, the current IC1is reduced compared to related approaches. As a result, the voltagerequired to turn on the transistor Q1 in FIG. 2 increases. Accordingly,a holding voltage for turning on the SCR which includes the transistorsQ1 and Q2 increases as well, and the SCR will not be easily turned on inan undesired condition. As a result, integrated circuits including theSCR will not be conducted in an undesired condition, and will beprevented from being destructed due to undesired operation. Latch-upimmunity for the integrated circuits including the SCR is thus improved.

The resistive load 220 and the collectors C21 and C22 of the transistorQ2 in the circuit 200 in FIG. 2 are given for illustrative purposes.Various numbers of resistive loads and collectors of the transistor Q2in the circuit 200 are within the contemplated scope of the presentdisclosure.

In some alternative embodiments, the transistor Q1 has four terminals,and the transistor Q2 has four terminals. Reference is made to FIG. 3.FIG. 3 is a schematic diagram of a circuit 300 in accordance withvarious embodiments of the present disclosure. With respect to theembodiments of FIG. 3, like elements in FIG. 1 are designated with thesame reference numbers for ease of understanding. The circuit 300includes transistors Q1 and Q2, the resistors R1 and R2, and tworesistive loads 310 and 320. For illustration, compared to the circuit100 in FIG. 1, the transistor Q2 has a first collector C21 coupled tothe base B1 of the transistor Q1 and the resistor R1, and a secondcollector C22 coupled to the reference voltage terminal through theresistive load 320. Explained in a different way, the transistor Q1 hastwo collectors C11 and C12, and the transistor Q2 has two collectors C21and C22. Similar to the circuit 100, the transistors Q1 and Q2 operateas a silicon controlled rectifier (SCR).

Operation with respect to the circuit 300 in FIG. 3 is similar to thecircuits 100 and 200 in FIGS. 1 and 2. The minority carriers aredischarged through the first collector C11 of the transistor Q1 and theresistor R2 to the reference voltage terminal VSS, and also through thesecond collector C12 of the transistor Q1 and the resistive load 310 tothe reference voltage terminal VSS. Moreover, the minority carriers aredischarged through the first collector C21 of the transistor Q2 and theresistor R1 to the reference voltage terminal VDD, and also through thesecond collector C22 of the transistor Q2 and the resistive load 320 tothe reference voltage terminal VDD.

In some approaches, minority carriers are mostly discharged throughpaths including, for example, the first collector C11 of the transistorsQ1 and the first collector C21 of the transistor Q2 as illustrated inFIG. 3. Accordingly, a parasitic SCR in integrated circuits is easilyturned on in a way as discussed above. As a result, the integratedcircuits including the parasitic SCR can be easily conducted in anundesired condition (also referred to as “latch-up” in some approaches),which leads to the destruction of the integrated circuits in somesituations.

Compared to the above approaches, to discharge the minority carriers,two shunt paths including, for illustration in FIG. 3, the secondcollector C12 of the transistor Q1, the resistive loads 310, the secondcollector C22 of the transistor Q2 and the resistive loads 320 areprovided in the embodiments of the present application. As discussedabove, the currents IC2 flowing through the shunt paths are alsogenerated when the minority carriers are discharged. As a result,integrated circuits including the SCR will not be conducted in anundesired condition, and will be prevented from being destructed due toundesired operation. Latch-up immunity for the integrated circuitsincluding the SCR is thus improved.

The resistive loads 310, 320, the collectors C11 and C12 of thetransistor Q1, and the collectors C21 and C22 of the transistor Q2 inthe circuit 300 in FIG. 3 are given for illustrative purposes. Variousnumbers of resistive loads and collectors of the transistors Q1 and Q2in the circuit 300 are within the contemplated scope of the presentdisclosure.

In some embodiments, resistances of the resistive loads 110, 220, 310and 320 range from about tens ohm to about 2000 ohm. The resistances ofthe resistive loads are given for illustrative purposes. Variousresistances of the resistive loads 110, 220, 310 and 320 are within thecontemplated scope of the present disclosure. For example, in variousembodiments, the resistance of each one of the resistive loads 110, 220,310 and 320 is set such that charges are allowed to be dischargedthrough the corresponding resistive load.

Reference is made to FIGS. 3 and 4. FIG. 4 is a cross-sectional diagramof a semiconductor device 400 of the circuit 300 in FIG. 3, inaccordance with some embodiments of the present disclosure. Thesemiconductor device 400 includes a substrate 410, a well 420 of a firstconductivity type, a well 430 of a second conductivity type, regions421, 432, 433 and 434 of the first conductivity type, regions 422, 423,424 and 431 of the second conductivity type, insulators 425, andresistive loads 310 and 320. The region 421 of the first conductivitytype and the regions 422, 423 and 424 of the second conductivity typeare disposed in the well 420 of the first conductivity type. The region431 of the second conductivity type and the regions 432, 433 and 434 ofthe first conductivity type are disposed in the well 430 of the secondconductivity type. The resistive load 310 is coupled between the region424 of the second conductivity type and a reference voltage terminalVSS, and the resistive load 320 is coupled between the region 434 of thefirst conductivity type and a reference voltage terminal VDD. In someembodiments with reference to FIG. 4, a transistor M1 is formed withrespect to the transistor Q1, and a transistor M2 is formed with respectto the transistor Q2. For illustration, the regions 422 and 423 and thewell 420 are included in a structure operating as the transistor M1, andthe regions 432 and 433 and the well 430 are included in a structureoperating as the transistor M2. In some embodiments, each one of thetransistors M1 and M2 is a metal oxide semiconductor field effect(MOSFET) transistor.

In some embodiments, the first conductivity type is N-type, the secondconductivity type is P-type, and the substrate 410 is a P-typesubstrate. Accordingly, the regions 421, 432, 433 and 434 are N-typeactive regions, and the regions 422, 423, 424 and 431 are P-type activeregions. The regions 422 and 423 of P-type and the well 420 of N-typeare included in a structure operating as a P-type metal oxidesemiconductor field effect (MOSFET) transistor M1. The regions 432 and433 of N-type and the well 430 of P-type are included in a structureoperating as an N-type metal oxide semiconductor field effect transistorM2. With reference to FIG. 3 and FIG. 4, the region 422 corresponds tothe emitter E of the transistor Q1, the well 420 corresponds to the baseB of the transistor Q1, the well 430 corresponds to the collector C1 ofthe transistor Q1, the region 424 corresponds to the collector C2 of thetransistor Q1, the region 432 corresponds to the emitter E of thetransistor Q2, the well 430 corresponds to the base B of the transistorQ2, the well 420 corresponds to the collector C1 of the transistor Q2,and the region 434 corresponds to the collector C2 of the transistor Q2.Accordingly, the region 422 of P-type, the well 420 of N-type and thewell 430 of P-type form the transistor Q1 in FIG. 3. Similarly, the well420 of N-type, the well 430 of P-type and the region 432 of P-type formthe transistor Q2 in FIG. 3. As above mentioned, the transistors Q1 andQ2 operate as a silicon controlled rectifier (SCR). Explained in adifferent way, the well 420 of N-type, the well 430 of P-type and theregion 432 of N-type that form a parasitic PNPN structure operate as thesilicon controlled rectifier (SCR). The resistor R1 has resistance ofthe well 420, and the resistor R2 has resistance of the substrate 410.As a result, minority carriers in the well 420 are discharged through apath of the region 424 and the resistive load 310 to the referencevoltage VSS, and minority carriers in the well 430 are dischargedthrough a path including the region 434 and the resistive load 320 tothe reference voltage terminal VDD. The first conductivity type and thesecond conductivity type are given for illustrative purposes. Variousconductivity types of the first conductivity type and the secondconductivity type are within the contemplated scope of the presentdisclosure. In some embodiments, the first conductivity type is P-type,the second conductivity type is N-type, and the reference voltageterminals VDD and VSS are interchanged.

In some embodiments, at least one of the resistive loads 110, 220, 310and 320 includes a metal line pattern or metal routing. In someembodiments, the metal line pattern indicates a pattern in a layout,which is implemented as the resistive load 110, 220, 310, 320, or thecombination. In some embodiments, the metal routing indicates a metalinterconnection, which is implemented as the resistive load 110, 220,310, 320, or the combination. Reference is made to FIG. 5. FIG. 5 is across-sectional diagram of a portion of the semiconductor device 400 inFIG. 4, together with a resistive load 540, in accordance with someembodiments of the present disclosure. With reference to FIG. 3 and FIG.5, the region 422 corresponds to the emitter E1 of the transistor Q1,the well 420 corresponds to the base B1 of the transistor Q1, and theregion 424 corresponds to the collector C12 of the transistor Q1. Withrespect to the embodiments of FIG. 5, like elements in FIG. 4 aredesignated with the same reference numbers for ease of understanding.

In some embodiments, the resistive load 540 coupled between the region424 and the reference voltage terminal VSS includes a metal line pattern545 (or metal routing in various embodiments), and the metal linepattern 545 has a resistance. As discussed above, for illustration, theregion 421 is an N-type active region, and the regions 422, 423 and 424are P-type active regions. The regions 422 and 423 of P-type and thewell of N-type are included in a structure operating as an P-type metaloxide semiconductor field effect (MOSFET) transistor M1. The minoritycarriers in the well 420 are discharged through a path of the region 424and the metal line pattern 545 to the reference voltage VSS. Explainedin a different way, the minority carriers in the base B1 of thetransistor Q1 in FIG. 3 are discharged through the path of the region424 and the metal line pattern 545 to the reference voltage VSS. As aresult, layout area for preventing latch-up is effectively savedcompared to the aforementioned approaches, such as a guard ringstructure or a pick-up structure.

In alternative embodiments, compared to FIG. 5, the metal line pattern545 is coupled between the region 424 and the reference voltage terminalVDD (not shown in FIG. 5). For illustration, the first conductivity typeis P-type, the second conductivity type is N-type, and the substrate 410is P-type, and the regions 421 and 422 are coupled to the referencevoltage terminal VSS (not shown FIG. 5). The minority carriers in thewell 420 are discharged through a path of the region 424 and the metalline pattern 545 to the reference voltage VDD (not shown in FIG. 5).Explained in a different way, the minority carriers in the base B2 ofthe transistor Q2 in FIG. 2 are discharged through the path of theregion 424 and the metal line pattern 545 to the reference voltage VDD.

In some embodiments, the resistive load 110, 220, 310, 320 or thecombination thereof includes a transistor to be turned on. Reference ismade to FIG. 6. FIG. 6 is a cross-sectional diagram of a portion of thesemiconductor device 400 in FIG. 4, together with a resistive load 640,in accordance with some embodiments of the present disclosure. Withrespect to the embodiments of FIG. 6, like elements in FIG. 4 aredesignated with the same reference numbers for ease of understanding.

Compared to the semiconductor device 500 in FIG. 5, the semiconductordevice 600 further includes a well 630 and regions 631, 632 and 633. Theregions 631, 632 and 633 are disposed in the well 630. For illustration,the resistive load 640 is coupled between the region 424 and thereference voltage terminal VSS, the first conductivity type is N-type,the second conductivity type is P-type, and the substrate 410 is P-type.The regions 421, 632 and 633 are N-type active regions, and the regions422, 423, 424 and 631 are P-type active regions. The regions 422 and 423of P-type and the well 420 of N-type are included in a structureoperating as an P-type metal oxide semiconductor field effect (MOSFET)transistor M1. The regions 632 and 633 of N-type and the well 630 ofP-type are included in a structure operating as an N-type metal oxidesemiconductor field effect (MOSFET) transistor M3 to be turned on. Theregion 633 of N-type in the transistor M3 is coupled to the region 424of P-type, and the region 632 of N-type in the transistor M3 is coupledto the reference voltage terminal VSS. As a result, the minoritycarriers in the well 420 are discharged through a path of the region 424and the transistor M3 to the reference voltage VSS. Explained in adifferent way, the minority carriers in the base B1 of the transistor Q1in FIG. 1 are discharged through the path of the region 424 and thetransistor M3 to the reference voltage VSS. As a result, layout area forpreventing latch-up is effectively saved compared to the aforementionedapproaches, such as a guard ring structure or a pick-up structure.

In alternative embodiments, compared to FIG. 6, the resistive load 640is coupled between the region 424 and the reference voltage terminal VDD(not shown in FIG. 6). For illustration, the first conductivity type isP-type, the second conductivity type is N-type, the substrate 410 isP-type, and the regions 421 and 422 are coupled to the reference voltageterminal VSS (not shown in FIG. 6). The minority carriers in the well420 are discharged through a path of the region 424 and the transistorM3 to the reference voltage VDD (not shown in FIG. 6). Explained in adifferent way, the minority carriers in the base B2 of the transistor Q2in FIG. 2 are discharged through the path of the region 424 and thetransistor M3 to the reference voltage VDD.

Reference is made to FIG. 7. FIG. 7 is a cross-sectional diagram of aportion of the semiconductor device 400 in FIG. 4, together with aresistive load 740, in accordance with some embodiments of the presentdisclosure. With respect to the embodiments of FIG. 7, like elements inFIG. 4 are designated with the same reference numbers for ease ofunderstanding.

Compared to the semiconductor device 500 in FIG. 5, the semiconductordevice 700 further includes a region 731 disposed in the well 420. Forillustration, the resistive load 740 coupled to the reference voltageterminal VSS, the first conductivity type is N-type, the secondconductivity type is P-type, and the substrate 410 is P-type. The region421 is an N-type active region, and the regions 422, 423, 424 and 731are P-type active regions. The regions 422 and 423 of P-type and thewell 420 of N-type are included in a structure operating as an P-typemetal oxide semiconductor field effect (MOSFET) transistor M1. Theregion 424 and 731 of P-type and the well 420 of N-type are included ina structure operating as a P-type metal oxide semiconductor field effect(MOSFET) transistor M3 to be turned on. The region 731 of P-type in thetransistor M3 is coupled to the reference voltage terminal VSS. As aresult, the minority carriers in the well 420 are discharged through apath of the transistor M3 to the reference voltage VSS. Explained in adifferent way, the minority carriers in the base B1 of the transistor Q1in FIG. 1 are discharged through the path of the transistor M3 to thereference voltage VSS. As a result, layout area for preventing latch-upis effectively saved compared to the aforementioned approaches, such asa guard ring structure or a pick-up structure.

In alternative embodiments, compared to FIG. 7, the resistive load 740is coupled to the reference voltage terminal VDD (not shown in FIG. 7).For illustration, the first conductivity type is P-type, the secondconductivity type is N-type, the substrate 410 is P-type, and theregions 421 and 422 are coupled to the reference voltage terminal VSS(not shown in FIG. 7). The minority carriers in the well 420 aredischarged through a path of the transistor M3 to the reference voltageVDD (not shown in FIG. 7). Explained in a different way, the minoritycarriers in the base B2 of the transistor Q2 in FIG. 2 are dischargedthrough the path of the transistor M3 to the reference voltage VDD.

Reference is made to FIG. 8. FIG. 8 is a cross-sectional diagram of aportion of the semiconductor device 400 in FIG. 4, together with aresistive load 840, in accordance with some embodiments of the presentdisclosure. With respect to the embodiments of FIG. 8, like elements inFIG. 4 are designated with the same reference numbers for ease ofunderstanding.

Compared to the semiconductor device 500 in FIG. 5, the semiconductordevice 800 further includes wells 830 and 850, and regions 831, 832 and833. The regions 831, 832 and 833 are disposed in the well 830, and thewell 850 is disposed between the wells 420 and 830. For illustration,the resistive load 840 is coupled between the region 424 and thereference voltage terminal VSS, the first conductivity type is N-type,the second conductivity type is P-type, the well 830 is N-type, the well850 is P-type, and the substrate 410 is P-type. The regions 421 and 831are N-type active regions, and the regions 422, 423, 424, 832 and 833are P-type active regions. The regions 422 and 423 of P-type and thewell 420 of N-type are included in a structure operating as an P-typemetal oxide semiconductor field effect (MOSFET) transistor M1. Theregions 832 and 833 of P-type and the well 830 of N-type are included ina structure operating as an P-type metal oxide semiconductor fieldeffect (MOSFET) transistor M3 to be turned on. The region 833 of P-typein the transistor M3 is coupled to the region 424 of P-type, and theregion 832 of P-type in the transistor M3 is coupled to the referencevoltage terminal VSS. As a result, the minority carriers in the well 420are discharged through a path of the region 424 and the transistor M3 tothe reference voltage VSS. Explained in a different way, the minoritycarriers in the base B1 of the transistor Q1 in FIG. 1 are dischargedthrough the path of the region 424 and the transistor M3 to thereference voltage VSS. As a result, layout area for preventing latch-upis effectively saved compared to the aforementioned approaches, such asa guard ring structure or a pick-up structure.

In alternative embodiments, compared to FIG. 8, the resistive load 840is coupled between the region 424 and the reference voltage terminal VDD(not shown in FIG. 8). For illustration, the first conductivity type isP-type, the second conductivity type is N-type, the well 830 is P-type,the well 850 is N-type, the substrate 410 is P-type, and the regions 421and 422 are coupled to the reference voltage terminal VSS (not shown inFIG. 8). The minority carriers in the well 420 are discharged through apath of the region 424 and the transistor M3 to the reference voltageVDD (not shown in FIG. 8). Explained in a different way, the minoritycarriers in the base B of the transistor Q2 in FIG. 2 are dischargedthrough the path of the region 424 and the transistor M3 to thereference voltage VDD.

Reference is made to FIG. 9. FIG. 9 is a flow chart illustrating amethod 900 applied to the circuits 100, 200 and 300 illustrated in FIGS.1-3 or the semiconductor devices 400, 500, 600, 700 and 800 illustratedin FIGS. 4-8, in accordance with various embodiments of the presentdisclosure. For simplicity, the method 900 in FIG. 9 is discussed belowwith reference to the circuit 100 in FIG. 1. The method 900 includesoperations S901, S902, S903, S904 and S905. These operations are givenfor illustrative purposes. Additional operations are within thecontemplated scoped of the present disclosure. For example, in variousembodiments, additional operations are provided before, during, and/orafter the operations in the method 900, and/or some of the operationsdescribed are replaced or eliminated for other embodiments of the method900.

With reference to the method 900 in FIG. 9 and FIG. 1, in operationS901, minority carriers are injected from the base-emitter (B-E)junction of the transistor Q1, when a trigger source (not shown) isgenerated to turn on the transistor Q1.

With reference to the method 900 in FIG. 9 and FIG. 1, in operationS902, the minority carriers are discharged through the first collectorC1 of the transistor Q1 and the resistor R2 to the reference voltageterminal VSS such that the current IC1 is generated accordingly.

With reference to the method 900 in FIG. 9 and FIG. 1, in operationS903, the minority carriers are discharged through the second collectorC2 of the transistor Q1 and the resistive load 110 to the referencevoltage terminal VSS such that the current IC2 is generated accordingly.

The sequence of operation S902 and operation S903 illustrated in FIG. 9are only given for illustrative purposes. Various sequences of operationS902 and operation S903 are within the contemplated scope of the presentdisclosure. For example, operation S902 and operation S903 areeffectively performed at the same time in various embodiments.

With reference to the method 900 in FIG. 9 and FIG. 1, in operationS904, with the current IC1 flowing through the resistor R2, a voltage atthe base B of the transistor Q2 is generated.

With reference to the method 900 in FIG. 9 and FIG. 1, in operationS905, if the base-emitter voltage VBE of the transistor Q2 is sufficientfor the transistor Q2 to turn on, the transistor Q2 will be turned on.Accordingly, a silicon controlled rectifier (SCR) including thetransistors Q1 and Q2 will be turned on to operate.

For simplicity, the method 900 corresponding to the circuit 100 in FIG.1 is discussed above. Methods corresponding to the circuits 200 and 300in FIGS. 2 and 3 include operations corresponding to those in the method900 in FIG. 9, and thus they are not detailed herein.

While the methods provided herein are illustrated and described above asa series of acts or events, it will be appreciated that the illustratedordering of such acts or events are not to be interpreted in a limitingsense. The operations are not necessarily performed in the orderdescribed. For example, some acts occur in different orders and/orconcurrently with other acts or events apart from those illustratedand/or described herein. In addition, not all illustrated acts may berequired to implement one or more aspects or embodiments of thedescription herein. Further, in some embodiments, one or more of theacts depicted herein is carried out in one or more separate acts and/orphases. Alternatively stated, the order of the operations disclosed inthe present disclosure are able to be changed, or the operations areable to be executed simultaneously or partially simultaneously asappropriate, in accordance with the spirit and scope of variousembodiments of the present disclosure.

Based on the above embodiments, the minority carriers in the base of thetransistor Q1 and/or the transistor Q2 are discharged through at leastone shunt path of the resistive load 110 and/or the resistive load 220to the reference voltage VSS and/or the reference voltage terminal VDDin the present disclosure. Therefore, the base-emitter voltage VBE ofthe transistor Q1 and/or the base-emitter voltage VBE of the transistorQ2 required for turning on the silicon controlled rectifier (SCR) areincreased. Compared to the aforementioned approaches, latch-up immunityis effectively improved and the layout area is saved in the presentdisclosure.

Also disclosed is a semiconductor device. The semiconductor deviceincludes a first region, a second region, a third region, a fourthregion, a fifth region, a first resistive load and a second resistiveload. The first region is configured to operate as a first terminal of afirst transistor, and coupled to a first reference voltage terminal. Thesecond region is configured to operate as a second terminal of the firsttransistor. The third region is included in a first structure operatingas the first transistor. The fourth region is configured to operate as afirst terminal of a second transistor, and coupled to a second referencevoltage terminal. The fifth region is configured to operate as a secondterminal of the second transistor. The first resistive load isconfigured to couple the second region to the second reference voltageterminal. The second resistive load is configured to couple the fifthregion to the first reference voltage terminal. The first region, thethird region, the second region, the fifth region and the fourth regionare arranged in order, each of the first region, the second region andthe third region corresponds to a first conductive type, and each of thefourth region and the fifth region corresponds to a second conductivetype different from the first conductive type.

Also disclosed is a semiconductor device. The semiconductor deviceincludes a first well, a second well, a third well, a first region, asecond region, a third region, a fourth region and a fifth region. Thefirst well, the second well and the third well are arranged in order.The first region is disposed in the first well and coupled to a firstreference voltage terminal. The second region is disposed in the firstwell and coupled to the first reference voltage terminal. The thirdregion is disposed in the third well and coupled to the first referencevoltage terminal. The fourth region is disposed in the third well. Thefifth region is disposed in the first well and coupled to the fourthregion. Each of the first well, the third well, the second region, andthe third region corresponds to a first conductive type, and each of thesecond well, the first region, the fourth region, and the fifth regioncorresponds to a second conductive type different from the firstconductive type.

Also disclosed is a method. The method includes: discharging chargesfrom a first reference voltage terminal to a second reference voltageterminal through a first well, a first region disposed in the first welland a second region disposed in the first well; and discharging chargesfrom the first reference voltage terminal to the second referencevoltage terminal through the first well, a third region disposed in thefirst well and separated from the second region, a fourth regiondisposed in a second well and the second well in order. Each of thefirst well, the first region and the second well corresponds to a firstconductive type, each of the second region, the third region and thefourth region corresponds to a second conductive type different from thefirst conductive type, the third region is separated from the secondregion, and the first well is separated from the second well.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor device, comprising: a firstregion configured to operate as a first terminal of a first transistor,and coupled to a first reference voltage terminal; a second regionconfigured to operate as a second terminal of the first transistor; athird region included in a first structure operating as the firsttransistor; a fourth region configured to operate as a first terminal ofa second transistor, and coupled to a second reference voltage terminal;a fifth region configured to operate as a second terminal of the secondtransistor; a first resistive load configured to couple the secondregion to the second reference voltage terminal; and a second resistiveload configured to couple the fifth region to the first referencevoltage terminal, wherein the first region, the third region, the secondregion, the fifth region and the fourth region are arranged in order,each of the first region, the second region and the third regioncorresponds to a first conductive type, and each of the fourth regionand the fifth region corresponds to a second conductive type differentfrom the first conductive type.
 2. The semiconductor device of claim 1,further comprising: a sixth region included in a second structureoperating as the second transistor, disposed between the fourth regionand the fifth region, and corresponding to the second conductive type.3. The semiconductor device of claim 1, further comprising: a sixthregion coupled to the fourth region and the second reference voltageterminal, and corresponding to the first conductive type, wherein thefourth region is disposed between the sixth region and the fifth region.4. The semiconductor device of claim 3, further comprising: an insulatordisposed between and adjacent to the sixth region and the fourth region,to separate the sixth region and the fourth region from each other. 5.The semiconductor device of claim 1, further comprising: a sixth regioncoupled to the first region and the first reference voltage terminal,and corresponding to the second conductive type, wherein the firstregion is disposed between the sixth region and the third region.
 6. Thesemiconductor device of claim 1, further comprising: a wellcorresponding to the second conductive type, wherein the first resistiveload comprises a sixth region disposed in the well, and corresponding tothe first conductive type, and each of the first region, the secondregion, the third region, and the fourth region is disposed in the well.7. The semiconductor device of claim 1, further comprising: a first wellcorresponding to the second conductive type; and a second well separatedfrom the first well, and corresponding to the second conductive type,wherein the first resistive load comprises a sixth region disposed inthe second well, coupled to the first reference voltage terminal, andcorresponding to the second conductive type, and each of the firstregion, the second region, the third region, and the fourth region isdisposed in the first well.
 8. The semiconductor device of claim 7,wherein the first resistive load further comprises: a seventh regiondisposed in the second well, coupled to the second region, andcorresponding to the first conductive type; and an eighth regiondisposed in the second well, disposed between the seventh region and thesixth region, coupled to the second reference voltage terminal, andcorresponding to the first conductive type.
 9. A semiconductor device,comprising: a first well, a second well and a third well arranged inorder; a first region disposed in the first well and coupled to a firstreference voltage terminal; a second region disposed in the first welland coupled to the first reference voltage terminal; a third regiondisposed in the third well and coupled to the first reference voltageterminal; a fourth region disposed in the third well; and a fifth regiondisposed in the first well and coupled to the fourth region, whereineach of the first well, the third well, the second region, and the thirdregion corresponds to a first conductive type, and each of the secondwell, the first region, the fourth region, and the fifth regioncorresponds to a second conductive type different from the firstconductive type.
 10. The semiconductor device of claim 9, furthercomprising: a fourth well adjacent to the first well; and a sixth regiondisposed in the fourth well, and coupled to the first reference voltageterminal through a resistive load.
 11. The semiconductor device of claim9, further comprising: a sixth region disposed in the third well,disposed between the third region and the fifth region, and coupled to asecond reference voltage terminal different from the first referencevoltage terminal.
 12. The semiconductor device of claim 11, furthercomprising: a fourth well adjacent to the first well; and a seventhregion disposed in the fourth well, and coupled to the second referencevoltage terminal, wherein each of the fourth well and the seventh regioncorresponds to the first conductive type.
 13. The semiconductor deviceof claim 12, further comprising: an eighth region disposed in the fourthwell, coupled to the second reference voltage terminal, andcorresponding to the second conductive type.
 14. The semiconductordevice of claim 13, further comprising: a ninth region disposed in thefourth well, disposed between the eighth region and the fifth region,coupled to the first reference voltage terminal through a resistiveload, and corresponding to the second conductive type.
 15. Thesemiconductor device of claim 14, further comprising: a tenth regiondisposed in the fourth well, disposed between the eighth region and theninth region, and corresponding to the second conductive type, whereinthe tenth region and the eighth region are included in a structureoperating as a transistor.
 16. A method, comprising: discharging chargesfrom a first reference voltage terminal to a second reference voltageterminal through a first well, a first region disposed in the first welland a second region disposed in the first well; and discharging chargesfrom the first reference voltage terminal to the second referencevoltage terminal through the first well, a third region disposed in thefirst well and separated from the second region, a fourth regiondisposed in a second well and the second well in order, wherein each ofthe first well, the first region and the second well corresponds to afirst conductive type, each of the second region, the third region andthe fourth region corresponds to a second conductive type different fromthe first conductive type, the third region is separated from the secondregion, and the first well is separated from the second well.
 17. Themethod of claim 16, further comprising: discharging charges from thesecond reference voltage terminal to the first reference voltageterminal through a third well adjacent to the first well, a fifth regiondisposed in the third well and a sixth region disposed in the thirdwell, wherein the fifth region and the sixth region are separated fromeach other.
 18. The method of claim 17, further comprising: dischargingcharges from the second reference voltage terminal to the firstreference voltage terminal through the third well and a seventh regiondisposed in the third well in order, wherein each of the sixth regionand the seventh region corresponds to the first conductive type, andeach of the fifth region and the third well corresponds to the secondconductive type.
 19. The method of claim 16, further comprising:discharging charges from the first reference voltage terminal to thesecond reference voltage terminal through the second well and a sixthregion disposed in the second well in order.
 20. The method of claim 19,further comprising: coupling the first reference voltage terminal to aseventh region disposed in the second well, wherein the sixth region isdisposed between the seventh region and the fourth region, and theseventh region corresponds to the first conductive type.